VLSI Implementation of Neural Network
نویسندگان
چکیده
This paper proposes a novel approach for an optimal multi-objective optimization for VLSI implementation of Artificial Neural Network (ANN) which is area-power-speed efficient and has high degree of accuracy and dynamic range. A VLSI implementation of feed forward neural network in floating point arithmetic IEEE-754 single precision 32 bit format is presented that makes the use of digital weights and digital multiplier based on bit serial architecture. Simulation results with 45 nm & 90 nm tech file on Synopsis Design Vision Tool, Aldec’s Active HDL tool, Altera’s Quartus tool & MATLAB showed that the bit serial architecture (TYPE III) based multiplier implementation and use of floating point arithmetic (IEEE -754 Single Precision format) in ANN realization may provide a good multi-objective solution for VLSI implementation of ANN. Keyword — Artificial Neural Network (ANN), bit serial architecture (type III) based multiplier, array multiplier, floating point arithmetic, multi-layered artificial neural network (MNN), Neural Network (NN), multi-layer perceptron (MLP).
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